On Friday, Intel demoed its Tigerton processor--a quad-core, Core2-based beast that sits on a platform with 4 independent buses. Now that is definitely going to make some heads turn.
Let me reiterate, the Core2 microarchitecture is vastly superior to the K8 micro-architecture, with K8L addressing only some of the gaps. The only upper edge that K8L has is its interconnect architecture and integrated memory controller, that gives it better memory bandwidth and lower latency. However, with four independent FSBs, Tigerton is to 4P what Woodcrest is to DP, and we have already seen what Woodcrest is capable of (AMD even acknowledged that they are facing competition in 2P with Intel claiming they regained some lost market share in 2P). The four independent buses will vastly alleviate Intel's bandwidth problem, while large caches and smart prefethers can mostly nullify the latency advantage. Esentially, I expect Tigerton to be the new king of 4P and rule them all for a while. K8L with HT3 can show some advantage in some memory-intensive loads, but with Barcelona stuck at three HT2 links, Tigerton will have full three to six months of unchallenged supremacy.
Why does it matter? Well, frankly I don't think it matters that much to Intel as far as revenues or profits are concerned. 4P is already niche. But considering how AMD is strongly reliant on its 4P business, it has potentil of making the marketplace more difficult for AMD.
And please, don't get started on vaporware argument. Intel has shown a Tigerton system running. All that AMD has shown in a wafer containing some huge K8L dies.
Monday, October 23, 2006
Sunday, October 01, 2006
Torrenza and 4S
I honestly think that 4S is reaching the end of the road. When you start putting so many cores into a single package, who needs 4P? 4P is already such a narrow market... The increasing power of 2P will put even more pressure on this already niche market!
Consider this for a moment: If Intel adds Dempsy-style internal bus to quad-core Penryn, then the 4 cores will look like just a single load to the FSB, and arguably, Intel will be able to pack two of these qaud-cores onto the same package (if the package has enough space). So, in theory, a Dempsy-style internal bus will allow Intel to have 8-core chips by the end of next year. If this happens (I understand that that is a big if, but Intel is desperate to claim sustained leadership, thus who knows), we are looking at 2P systems with 16 cores!! Going forward, rumors are that Intel will reintroduce its hyperthreading. That will put 32 logical processors on a 2P system. This is bound to make the 4P market ridiculously niche. So what does that mean? Does Intel really need the CSI? Afterall, the dual FSB is more than sufficient for the 2P market...
In my opinion, it does need CSI. The problem is not 4P or 8P--that is a dying breed. The real problem is Torrenza--AMD's ability to couple third-party processors with its own. At IDF, Intel announced that it will open up its FSB to third parties. Pardon my french, but who gives a f&*^ing @#$%? Why would anyone want to put their co-processor on an FSB that Intel is always in a hurry to upgrade? With HT, you can arguably negotiate the different links at different speeds, and hence the third parties do not have to upgrade their HT logic to keep up with AMD. On the other hand, since the entire FSB system will be limited by the speed of the slowest component, third parties have no choice but to run with Intel or be rendered obsolete. And that is exactly what they don't want. Thus, if Intel wants to provide a Torrenza-like capability, it needs a point-to-point interconnect that can be negotiated independently. FSB just won't cut it.
Does Intel need to provide a Torrenza-like solution? Frankly, I don't know. Today there are not many co-processor applications where the co-processor has to interact with the main processor on a clock-cycle-by-clock-cycle basis. But arguably, that is because, presently there is no technology that allows a co-processor to interact with the CPU that closely. AMD's Torrenza will make that possible for the first time--and who knows, it might even catch on? Intel cannot afford to ignore Torrenza, that's the bottom line. And that is why, it needs a cache-coherent point-to-point interconnect solution. Maybe it's CSI, maybe it's something else. But they need one for sure...
Consider this for a moment: If Intel adds Dempsy-style internal bus to quad-core Penryn, then the 4 cores will look like just a single load to the FSB, and arguably, Intel will be able to pack two of these qaud-cores onto the same package (if the package has enough space). So, in theory, a Dempsy-style internal bus will allow Intel to have 8-core chips by the end of next year. If this happens (I understand that that is a big if, but Intel is desperate to claim sustained leadership, thus who knows), we are looking at 2P systems with 16 cores!! Going forward, rumors are that Intel will reintroduce its hyperthreading. That will put 32 logical processors on a 2P system. This is bound to make the 4P market ridiculously niche. So what does that mean? Does Intel really need the CSI? Afterall, the dual FSB is more than sufficient for the 2P market...
In my opinion, it does need CSI. The problem is not 4P or 8P--that is a dying breed. The real problem is Torrenza--AMD's ability to couple third-party processors with its own. At IDF, Intel announced that it will open up its FSB to third parties. Pardon my french, but who gives a f&*^ing @#$%? Why would anyone want to put their co-processor on an FSB that Intel is always in a hurry to upgrade? With HT, you can arguably negotiate the different links at different speeds, and hence the third parties do not have to upgrade their HT logic to keep up with AMD. On the other hand, since the entire FSB system will be limited by the speed of the slowest component, third parties have no choice but to run with Intel or be rendered obsolete. And that is exactly what they don't want. Thus, if Intel wants to provide a Torrenza-like capability, it needs a point-to-point interconnect that can be negotiated independently. FSB just won't cut it.
Does Intel need to provide a Torrenza-like solution? Frankly, I don't know. Today there are not many co-processor applications where the co-processor has to interact with the main processor on a clock-cycle-by-clock-cycle basis. But arguably, that is because, presently there is no technology that allows a co-processor to interact with the CPU that closely. AMD's Torrenza will make that possible for the first time--and who knows, it might even catch on? Intel cannot afford to ignore Torrenza, that's the bottom line. And that is why, it needs a cache-coherent point-to-point interconnect solution. Maybe it's CSI, maybe it's something else. But they need one for sure...
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