On Friday, Intel demoed its Tigerton processor--a quad-core, Core2-based beast that sits on a platform with 4 independent buses. Now that is definitely going to make some heads turn.
Let me reiterate, the Core2 microarchitecture is vastly superior to the K8 micro-architecture, with K8L addressing only some of the gaps. The only upper edge that K8L has is its interconnect architecture and integrated memory controller, that gives it better memory bandwidth and lower latency. However, with four independent FSBs, Tigerton is to 4P what Woodcrest is to DP, and we have already seen what Woodcrest is capable of (AMD even acknowledged that they are facing competition in 2P with Intel claiming they regained some lost market share in 2P). The four independent buses will vastly alleviate Intel's bandwidth problem, while large caches and smart prefethers can mostly nullify the latency advantage. Esentially, I expect Tigerton to be the new king of 4P and rule them all for a while. K8L with HT3 can show some advantage in some memory-intensive loads, but with Barcelona stuck at three HT2 links, Tigerton will have full three to six months of unchallenged supremacy.
Why does it matter? Well, frankly I don't think it matters that much to Intel as far as revenues or profits are concerned. 4P is already niche. But considering how AMD is strongly reliant on its 4P business, it has potentil of making the marketplace more difficult for AMD.
And please, don't get started on vaporware argument. Intel has shown a Tigerton system running. All that AMD has shown in a wafer containing some huge K8L dies.
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17 comments:
Yeah 4 buses, 1066mhz to each socket, sounds good but that's just 266mhz per core. Another words 2/3 what your Williamette Netbust FSB was. And as you've said this is Core 2 goodness, these cores are a little wider than P4. So unless you have no plans of actually loading those cores, you have to hope the 64 MB Snoop Cache can do a good job of keeping up with that 32 GB/s mem throughput. All to make up for a bad interconnect, simply because they don't want to admit its outdated.
http://www.siliconvalleysleuth.com/2006/10/intel_shines_on.html
Here is also a video of it.
http://www.intel.co.jp/jp/business/japan/event/IDF_2006/pix/02-08.jpg
They also have shown a die[not wafer] since Spring?
He didn't say K8L was vaporware but that those that would claim Tigerton to be should consider AMD and Barcelona:) Sorry, semantics:p
http://www.dailytech.com/article.aspx?newsid=3448
"to demonstration our next-generation processor core, in a native quad-core implementation, before the end of the year."
Intel might not have shown quad core on a single die but they've shown it on a single socket:) I wonder, how different would it be for AMD to show Barcelona now compared to December.. Stop Intel defects earlier yet also at the same time, delaying current sales.
http://www.hothardware.com/image_popup.cfm?image=big_amd4x4loaded.jpg&articleid=884&t=a
BTW, I found an actual pic of 4x4 using those programs HotHardware mentioned:) Impressive that at 100%, it can still tack on the other programs.
Ashman said...
I'm sorry to do this, but a vaporware argument is in order being that this seems to me to be the first time you or anyone I know has introduced the argument the K8L is vaporware.
Interesting!! AMD fans were calling Core 2 AFTER it was launched. The claims were, it was not available for practical use, and that's why it was called vaporware.
Besides, I did not call K8L vaporware. I said, "Do not get me started on vaporware argument", meaning that Tigerton is not vaporware. It is a real working chip that Intel has demonstrated.
Another words 2/3 what your Williamette Netbust FSB was
First off, Intel is claiming 1333. So it will be twice that of Tulsa, per core.
Second, as I have said numerous times, Core 2 architecture is not THAT constrained by bandwidth/latency. Look at Kentsfield. Rahul Sood reported on his blog that the processor is nothing short of impressive. The reason Core 2 is not constrained is that it has a huge cache and smart prefetchers. This is not the most cost-effective way of improving the memory throughput, but it can do the trick.
Also, I searched a lot, but I couldn't find any specifications as to what the cache size is going to be on Tigerton. But considering how lavishly Intel has been blessing their MP Xeons with cache, I wouldn't be surprised if it is some obscenely huge number.
The bottomline is, Tulsa is already giving better TPC and TPC$ numbers than Opteron. Tigerton will improve that a huge factor.
BTW, I found an actual pic of 4x4 using those programs HotHardware mentioned:) Impressive that at 100%, it can still tack on the other programs.
AMD 4x4 is neat--HT allows them to that. However, pricing-wise it does not make too much sense. Price it too low, and it can undercut low-end servers. Price it too high, and Kentsfield knocks it out.
You still haven't addressed the issue of thinking barcelona wont be k8l.
When did I say Barcelona won't be K8L? What I said was, until 2008, AMD won't have HT3.0. Barcelona is K8L core with HT2.0. I believe, it still has 3 HT links, and hence, complete connectivity in 4P and 8P is not possible. Even if it has more HT links, it certainly cannot have 8 16-bit HT2.0 links. Since those links cannot be split into 2 8-bit each, 8P solutions would still require the kludge of 1-hop away.
So, to summarize: I know that Barcelona is K8L core, but INQ reported that it is going to be on HT2.0, not 3.0. HT 3.0 and DC 2.0 is scheduled for Q108.
I will dig out the INQ link if you want me to, but Charlie (probably the only INQ writer who understands architecture) had written a long article on Barcelona--what it is and what it is not.
TPC? I'm sorry, I'm not familiar with this term, but I was under the impression that Tulsa performed poorly and was ridiculously hot.
TPC: Transaction-processing Performance Council. They have a wide range of benchmarks (TPC-C, TPC-H, etc)for transaction-processing stuff, and on servers of this size (4P and above), people typically only care for these benchmarks.
Yes Tulsa is hot. But on TPCC it beats (or at least beat when I checked last time) 4P opteron on TPCC and TPCC$. It is not ideal for everyone. But if you do not care about power, and you run transaction-type workloads (banks, etc), and you need extreme reliability (protection against cache errors, etc), Tulsa is for you. On many other benches Opteron will beat Tulsa handily.
Does anyone have anything showing how Core2s perform in terms of changes in their fsb? I think this would be a good way to put this argument to rest, as the test would scale quite nicely.
Tom's Hardware had reviewed Kentsfield (2 C2D on one chip--google for Kentsfield review and you will find the link). They tested it at the same speed with 1066 and 1333 FSB. They found no advantage in going to 1333 FSB. That clearly shows that even 1066 FSB is good enough to feed 2 C2Ds. Now certain memory-intensive workloads will be there, but mostly, it appears that the FSB is not constraining C2D.
Also, I do not understand your argument against large caches. A large cache is a problem only if the size reduces its speed. Intel caches are blazing fast (14-cycle L2 latency at 3GHz and above). Also, on a cache conflict, you only thrash the line (which is typically 64 bytes--fixed since pentium days), and hence larger cache size does not cause more cache conflicts.
Have you heard of AM2+? It'll be HT3.0 with Barcelona:)
I haven't seen anything to indicate that Tigerton would take the lead over Opteron in 4P, and even then, all we wear is how amazing[numbers anyone?] AMD is compared to Intel in that segment. Especially with servers, may I suggest waiting?:) Even then, who cares:p
Your direct connect 2.0 argument is even more pointless, if quad core somehow were able to decrease demand for 4p. They wont need it if there's less demand for situations where it's actually used.
You are essentially echoing back my argument. My argument is, in 2P, AMD is already challenged. 4C makes 4P more niche. Even in this niche, Intel is striking back with Tigerton. Thus, all this has huge potential to make life very difficult for AMD.
actually what they meant was Paper Launch
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